How to realize encoder function in VHDL

There are many ways in which encoder function can be implemented in VHDL. Here 4 different techniques with VHDL codes are provided.

Suppose we to design an encoder which outputs y with sel input as follows,

when sel is 00, y is 1110
when sel is 01, y is 1101
when sel is 10, y is 1011
when sel is 11, y is 0111

So the input sel is 2 bit and output y is 4 bit. The the encoder entity can be declared as follows-

entity encoder is
    port(
    sel : in std_logic_vector(1 downto 0);
    y : out std_logic_vector(3 downto 0)
    );
end encoder;

Now there are different ways to realize the encoder function.

1. Using if then elsif statements inside a process

architecture arch1 of encoder is
begin
    process(sel)
    begin
        y <= (yrange => 1);
        if (sel = "00") then y(0) <= 0;
        elsif (sel = "01") then y(1) <= 0;
        elsif (sel = "10") then y(2) <= 0;
        else y(3) <= 0;
        end if;
    end process;
end arch1;

2. Using case statement inside a process

architecture arch2 of encoder is
begin
    process(sel)
    begin
        y <= (yrange => 1);
        case sel is
            when "00" => y(0) <= 0;
            when "01" => y(1) <= 0;
            when "10" => y(2) <= 0;
            when others => y(3) <= 0;
        end case;
    end process;
   
end arch2;

3. Using simple select statement

architecture arch3 of encoder is
begin
    with sel select
    y <= "1110" when "00",
    "1101" when "01",
    "1011" when "10",
    "0111" when others;
end arch3;

4. Using conversion of sel inputs bits to integer and setting it to 0

architecture arch4 of encoder is
begin
    process(sel)
    begin
        y <= (yrange => 1);
        y(to_integer(unsigned(sel))) <= 0;
    end process;
end arch4;

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